Semiconductor devices, such as integrated circuits, are typically formed on a section of a wafer of semiconductor material, such as silicon. The wafer includes multiple sections where each section is called a die. For example, a wafer having an eight-inch diameter may include up to 600 individual dies. Each die contains an integrated circuit device commonly referred to as a chip.
The surface geometry of the various integrated-circuit components on a die is defined photographically. For example, the surface may be coated with a photosensitive layer and then exposed to light passing through a master pattern on a photographic plate, e.g., photo mask. The main body of the photo mask is a flat and transparent glass plate that defines the circuit pattern which may be a magnified replica (for example, 4×) of the image to be transferred to the surface. The transfer of the image from the photo mask to the surface of the wafer is accomplished through the use of various wavelengths, such as UV light, and a photoresist. Photoresists are chemical compositions containing a light-sensitive material in suspension. Photoresists are coated on the wafer using a variety of techniques, e.g., contact printing, spinning.
Anomalies in the integrated circuit may be detected by using a variety of techniques such as by scanning an electron or ion beam over the surface of the integrated circuit and detecting secondary charged particles. Anomalies, as used herein, may refer to either defects caused by manufacturing system problems, defects that occur without a systematic cause, or design defects. In order to determine the impact of the identified anomalies, the position of the anomalies may have to be identified in a design layout of the integrated circuit.
Typically, the anomalies are identified in the integrated circuit by manually aligning and positioning the design layout and the image of the integrated circuit. Since there is a manual alignment of the integrated circuit and the design layout, the identification of the location of the anomaly in the design layout may be subject to human error. Further, multiple tools designed by different vendors are used to investigate the anomaly and may have different reference systems. Hence, a manual coordination of the integrated circuit and the design layout may have to be performed for multiple tools.
If the anomaly is located in a critical area of the integrated circuit, accurate identification of the anomaly may be particularly important. Critical areas may correspond to areas of the integrated circuit that have the tightest performance limits relative to a nominal design specification. If the anomaly is incorrectly identified as being located outside a critical area, then the impact of the anomaly may not be fully realized. Consequently, the analysis of the impact of the anomaly may be deficient.
Further, anomalies may also be assessed by classifying the anomalies in certain categories based on features of the anomaly. For example, anomalies that contain certain characteristics may be classified in particular categories. However, by categorizing anomalies based on their own characteristics, the impact of the anomaly on surrounding circuitry is not assessed.
Therefore, there is a need in the art to automatically and reliably align the integrated circuit and the design layout across multiple tools designed by different vendors. Further, there is a need in the art to more fully assess the impact of the anomalies identified in the integrated circuits.